{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9748359","patent":{"patent_number":"US-9748359","title":"Vertical transistor bottom spacer formation","assignee":null,"inventors":[],"filing_date":"2016-10-27T00:00:00.000Z","publication_date":"2017-08-29T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":20,"abstract":"A silicon layer is formed on a surface of each bottom source/drain region that is present at the footprint of a semiconductor fin. A first set of atoms (nitrogen atoms or carbon atoms) and a second set of atoms (boron atoms and/or carbon atoms) are then ion implanted into the silicon layer and the bottom source/drain regions. An anneal is then performed to convert the silicon layer into a bottom dielectric spacer that is composed of a reaction product of silicon, the first set of atoms and the second set of atoms, while converting each bottom source/drain region into a bottom source/drain structure that includes a first region and a second region. The second region is composed of a doped semiconductor material and at least one of the boron atoms and the carbon atoms; no measurable nitrogen tail and/or oxygen tail is present in the source/drain structures."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Vertical transistor bottom spacer formation","description":"A silicon layer is formed on a surface of each bottom source/drain region that is present at the footprint of a semiconductor fin. A first set of atoms (nitrogen atoms or carbon atoms) and a second se","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9748359","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9748359","citation_suggestion":"Patentable. \"Vertical transistor bottom spacer formation\" (US-9748359). https://patentable.app/patents/US-9748359","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9748359","json":"https://patentable.app/api/llm-context/US-9748359","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:38:00.994Z"}