{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9753524","patent":{"patent_number":"US-9753524","title":"Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modules","assignee":null,"inventors":[],"filing_date":"2016-09-23T00:00:00.000Z","publication_date":"2017-09-05T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to multiple processing modules, each having a first clock configuration and a second clock configuration. The dispatch module, at a first time, changes a first processing module included in the multiple processing modules from a first clock configuration to a second clock configuration. The dispatch module prohibits, at a second time within a predetermined time period and after the first time, a second processing module included in the multiple processing modules from changing from the first clock configuration to the second clock configuration if an indicator associated with a number of changes of the multiple processing modules between a first clock configuration and a second clock configuration within the predetermined time period and prior to the second time satisfies a criterion."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modules","description":"A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to multiple processing modules, each having a first clock configuration and a second clock confi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9753524","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9753524","citation_suggestion":"Patentable. \"Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modules\" (US-9753524). https://patentable.app/patents/US-9753524","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9753524","json":"https://patentable.app/api/llm-context/US-9753524","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:59:53.488Z"}