{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9753780","patent":{"patent_number":"US-9753780","title":"Topology-aware processor scheduling","assignee":null,"inventors":[],"filing_date":"2015-07-07T00:00:00.000Z","publication_date":"2017-09-05T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":18,"abstract":"In an example embodiment, a method of operating a task scheduler for one or more processors is provided. A topology of one or more processors is obtained, the topology indicating a plurality of execution units and physical resources associated with each of the plurality of execution units. A task to be performed by the one or more processors is received. Then a plurality of available execution units from the plurality of execution units is identified. An optimal execution unit is then determined, from the plurality of execution units, to which to assign the task, based on the topology. The task is then assigned to the optimal execution unit, after which the task is sent to the optimal execution unit for execution."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Topology-aware processor scheduling","description":"In an example embodiment, a method of operating a task scheduler for one or more processors is provided. A topology of one or more processors is obtained, the topology indicating a plurality of execut","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9753780","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9753780","citation_suggestion":"Patentable. \"Topology-aware processor scheduling\" (US-9753780). https://patentable.app/patents/US-9753780","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9753780","json":"https://patentable.app/api/llm-context/US-9753780","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:36:14.368Z"}