{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9753862","patent":{"patent_number":"US-9753862","title":"Hybrid replacement policy in a multilevel cache memory hierarchy","assignee":null,"inventors":[],"filing_date":"2016-10-25T00:00:00.000Z","publication_date":"2017-09-05T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":13,"abstract":"A data processing system includes an upper level cache memory and a lower level cache memory employing different replacement policies. The lower level cache memory provides a respective one of a plurality of counters for each of a plurality of cache lines in a particular congruence class. The lower level cache memory initializes a counter value for a cache line in the particular congruence class that was castout from the upper level cache memory based on an indication of whether the cache line was accessed in the upper level cache memory following installation in the upper level cache memory. The lower level cache memory selects a victim cache line from among the plurality of cache lines in the particular congruence class for eviction from the lower level cache memory by reference to counter values of the plurality of counters."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Hybrid replacement policy in a multilevel cache memory hierarchy","description":"A data processing system includes an upper level cache memory and a lower level cache memory employing different replacement policies. The lower level cache memory provides a respective one of a plura","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9753862","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9753862","citation_suggestion":"Patentable. \"Hybrid replacement policy in a multilevel cache memory hierarchy\" (US-9753862). https://patentable.app/patents/US-9753862","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9753862","json":"https://patentable.app/api/llm-context/US-9753862","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:20:46.205Z"}