{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9754669","patent":{"patent_number":"US-9754669","title":"Flash memory arrangement with a common read-write circuit shared by partial matrices of a memory column","assignee":null,"inventors":[],"filing_date":"2015-09-30T00:00:00.000Z","publication_date":"2017-09-05T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":6,"abstract":"A flash memory arrangement includes first memory cells for non-volatile memory of information and a read-write circuit. The read-write circuit includes a write latch, read amplifier, bit circuit pre-charge circuit, and databus interface, with the first memory cell being connected to a first bit circuit, word circuit, VSE circuit, and a select circuit, and the read-write circuit being connected to a column decoder, databus, and a read control signal circuit. A first memory column is arranged such that in a first partial matrix the first memory cell is arranged, in which a first select transistor, a memory transistor, and a second select transistor are arranged between the first bit circuit and a discharge hub. The second select transistor can be controlled by a global, non address-decoded read-write select circuit. At every bit circuit, a reference memory cell is arranged. A second partial matrix is provided equivalent to the first partial matrix."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Flash memory arrangement with a common read-write circuit shared by partial matrices of a memory column","description":"A flash memory arrangement includes first memory cells for non-volatile memory of information and a read-write circuit. The read-write circuit includes a write latch, read amplifier, bit circuit pre-c","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9754669","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9754669","citation_suggestion":"Patentable. \"Flash memory arrangement with a common read-write circuit shared by partial matrices of a memory column\" (US-9754669). https://patentable.app/patents/US-9754669","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9754669","json":"https://patentable.app/api/llm-context/US-9754669","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:46:54.603Z"}