{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9754893","patent":{"patent_number":"US-9754893","title":"Semiconductor structure and fabrication method thereof","assignee":null,"inventors":[],"filing_date":"2015-09-22T00:00:00.000Z","publication_date":"2017-09-05T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":10,"abstract":"Semiconductor structure and fabrication methods are provided. The semiconductor structure includes a first wafer having a first metal layer therein and having a first material layer thereon, and a second wafer having a second metal layer therein and having a second material layer thereon. An alignment process and a bonding process are preformed between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer. A heating process is performed on the first material layer and the second material layer to melt the first material layer and the second material layer to provide a second alignment accuracy between the first metal layer and second metal layer. The second alignment accuracy is greater than the first alignment accuracy."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor structure and fabrication method thereof","description":"Semiconductor structure and fabrication methods are provided. The semiconductor structure includes a first wafer having a first metal layer therein and having a first material layer thereon, and a sec","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9754893","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9754893","citation_suggestion":"Patentable. \"Semiconductor structure and fabrication method thereof\" (US-9754893). https://patentable.app/patents/US-9754893","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9754893","json":"https://patentable.app/api/llm-context/US-9754893","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:38:15.304Z"}