{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9760515","patent":{"patent_number":"US-9760515","title":"Shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY)","assignee":null,"inventors":[],"filing_date":"2015-04-06T00:00:00.000Z","publication_date":"2017-09-12T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F"],"num_claims":25,"abstract":"Methods and systems for shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY) are disclosed. In one aspect, an arbitration logic circuit is coupled to ports of a multi-port PHY sharing a phase locked loop (PLL). Upon receiving an indication that the shared PLL is to be reset, the arbitration logic circuit commands the ports sharing the PLL to enter a state in which any reset of the shared PLL would have minimal or no effect in their operations. In this manner, an integrated circuit (IC) including a multi-port PHY may be configured with only one PLL and associated clock generating logic to provide a clock signal for some or all of its ports, thus reducing its semiconductor area and power consumption. Furthermore, the ports of the multi-port PHY may operate independently from each other obviating any configuration and/or interoperability problems associated with having a shared PLL."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY)","description":"Methods and systems for shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY) are disclosed. In one aspect, an arbitration logic circuit is coupled to ports of a multi-port","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9760515","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9760515","citation_suggestion":"Patentable. \"Shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY)\" (US-9760515). https://patentable.app/patents/US-9760515","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9760515","json":"https://patentable.app/api/llm-context/US-9760515","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:36:52.413Z"}