{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9761304","patent":{"patent_number":"US-9761304","title":"Write-bitline control in multicore SRAM arrays","assignee":null,"inventors":[],"filing_date":"2016-09-27T00:00:00.000Z","publication_date":"2017-09-12T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G06F","G11C","G11C"],"num_claims":17,"abstract":"An integrated circuit includes a static random access memory array. The static random access memory array includes at least two cores, wherein only one of the cores is written at a time. The integrated circuit further includes a tristate driver. The tristate driver is configured to apply a high impedance state to one of the cores that is not being written. A corresponding electronic dataset product includes a description for the integrated circuit expressed in a hardware description language. A corresponding computer-implemented method generates an electronic description for the integrated circuit expressed in a hardware description language."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Write-bitline control in multicore SRAM arrays","description":"An integrated circuit includes a static random access memory array. The static random access memory array includes at least two cores, wherein only one of the cores is written at a time. The integrate","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9761304","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9761304","citation_suggestion":"Patentable. \"Write-bitline control in multicore SRAM arrays\" (US-9761304). https://patentable.app/patents/US-9761304","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9761304","json":"https://patentable.app/api/llm-context/US-9761304","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:28:24.335Z"}