{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9761540","patent":{"patent_number":"US-9761540","title":"Wafer level package and fabrication method thereof","assignee":null,"inventors":[],"filing_date":"2015-10-30T00:00:00.000Z","publication_date":"2017-09-12T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":11,"abstract":"A semiconductor device that includes a redistribution layer (RDL) is disclosed. A chip is mounted on the RDL within a chip mounting area. The RDL is electrically connected to the chip. A molding compound covers and encapsulates the chip. A first stress-relief feature is embedded in the molding compound within a peripheral area adjacent to the chip mounting area. A second stress-relief feature is embedded in the molding compound within the chip mounting area. The first stress-relief feature is composed of a first material. The second stress-relief feature is composed of a second material that is different from the first material."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Wafer level package and fabrication method thereof","description":"A semiconductor device that includes a redistribution layer (RDL) is disclosed. A chip is mounted on the RDL within a chip mounting area. The RDL is electrically connected to the chip. A molding compo","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9761540","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9761540","citation_suggestion":"Patentable. \"Wafer level package and fabrication method thereof\" (US-9761540). https://patentable.app/patents/US-9761540","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9761540","json":"https://patentable.app/api/llm-context/US-9761540","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T18:29:07.885Z"}