{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9761679","patent":{"patent_number":"US-9761679","title":"Performance optimized gate structures having memory device and logic device, the memory device with silicided source/drain regions that are raised with respect to silicided source/drain regions of the logic device","assignee":null,"inventors":[],"filing_date":"2016-03-15T00:00:00.000Z","publication_date":"2017-09-12T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":13,"abstract":"A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Performance optimized gate structures having memory device and logic device, the memory device with silicided source/drain regions that are raised with respect to silicided source/drain regions of the logic device","description":"A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method f","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9761679","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9761679","citation_suggestion":"Patentable. \"Performance optimized gate structures having memory device and logic device, the memory device with silicided source/drain regions that are raised with respect to silicided source/drain regions of the logic device\" (US-9761679). https://patentable.app/patents/US-9761679","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9761679","json":"https://patentable.app/api/llm-context/US-9761679","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:14:10.327Z"}