{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9761699","patent":{"patent_number":"US-9761699","title":"Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures","assignee":null,"inventors":[],"filing_date":"2015-01-28T00:00:00.000Z","publication_date":"2017-09-12T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":13,"abstract":"A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures","description":"A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9761699","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9761699","citation_suggestion":"Patentable. \"Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures\" (US-9761699). https://patentable.app/patents/US-9761699","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9761699","json":"https://patentable.app/api/llm-context/US-9761699","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:35:50.923Z"}