{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9762919","patent":{"patent_number":"US-9762919","title":"Chroma cache architecture in block processing pipelines","assignee":null,"inventors":[],"filing_date":"2014-08-28T00:00:00.000Z","publication_date":"2017-09-12T00:00:00.000Z","cpc_codes":["H04N","G06F","G06F","G06F","G06F","G06T","H04N","H04N","H04N","H04N","H04N","H04N","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Chroma cache architecture in block processing pipelines","description":"Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9762919","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9762919","citation_suggestion":"Patentable. \"Chroma cache architecture in block processing pipelines\" (US-9762919). https://patentable.app/patents/US-9762919","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9762919","json":"https://patentable.app/api/llm-context/US-9762919","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:47:49.796Z"}