{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9767248","patent":{"patent_number":"US-9767248","title":"Semiconductor having cross coupled structure and layout verification method thereof","assignee":null,"inventors":[],"filing_date":"2015-09-03T00:00:00.000Z","publication_date":"2017-09-19T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":19,"abstract":"A semiconductor device and a layout verification method of a semiconductor device are provided. The layout verification method includes forming a plurality of standard cells each having a first type of a cross coupled structure (XC) and a second type of the XC on a substrate of the semiconductor device, forming a plurality of first inverters in which the first type of the XC is activated in the a plurality of the standard cells and a plurality of second inverters in which the second type of the XC is activated in the a plurality of the standard cells and estimating an electrical characteristic of the first type of the XC or the second type of the XC by measuring a magnitude of a signal delay of the plurality of the first inverters or the plurality of the second inverters."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor having cross coupled structure and layout verification method thereof","description":"A semiconductor device and a layout verification method of a semiconductor device are provided. The layout verification method includes forming a plurality of standard cells each having a first type o","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9767248","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9767248","citation_suggestion":"Patentable. \"Semiconductor having cross coupled structure and layout verification method thereof\" (US-9767248). https://patentable.app/patents/US-9767248","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9767248","json":"https://patentable.app/api/llm-context/US-9767248","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:12:48.799Z"}