{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9767892","patent":{"patent_number":"US-9767892","title":"Memory elements with dynamic pull-up weakening write assist circuitry","assignee":null,"inventors":[],"filing_date":"2016-04-27T00:00:00.000Z","publication_date":"2017-09-19T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C"],"num_claims":19,"abstract":"Integrated circuits with an array of memory cells are provided. Each memory cell may include at least one pair of cross-coupled inverters, write access transistors, and optionally a separate read port. The cross-coupled inverters in each memory cell may have a positive power supply terminal. The positive power supply terminal of each memory cell along a given column in the array may be coupled to a corresponding pull-up transistor. The pull-up transistor may receive a control signal from a pull-up weakening control circuit. The control signal may be temporarily elevated during write operations and may otherwise be driven back down to ground to help optimize read performance. The pull-up weakening control circuit may be implemented using a chain of n-channel transistors or a resistor chain."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory elements with dynamic pull-up weakening write assist circuitry","description":"Integrated circuits with an array of memory cells are provided. Each memory cell may include at least one pair of cross-coupled inverters, write access transistors, and optionally a separate read port","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9767892","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9767892","citation_suggestion":"Patentable. \"Memory elements with dynamic pull-up weakening write assist circuitry\" (US-9767892). https://patentable.app/patents/US-9767892","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9767892","json":"https://patentable.app/api/llm-context/US-9767892","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:50:54.771Z"}