{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9767895","patent":{"patent_number":"US-9767895","title":"Semiconductor memory device and controlling method thereof","assignee":null,"inventors":[],"filing_date":"2016-09-16T00:00:00.000Z","publication_date":"2017-09-19T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"The control unit performs a first writing operation to obtain a first threshold voltage distribution, and a second writing operation to obtain a second threshold voltage distribution lower than the first threshold voltage distribution, and a third threshold voltage distribution higher than the first threshold voltage distribution. A verify reading operation is performed to determine whether any of the first to third threshold voltage distributions has been obtained. A step-up writing operation, in accordance with a result of the verify reading operation, increases a program voltage by a predetermined step-up width. The step-up writing operation, after start of the second writing operation, sets the step-up width to a first step-up width, and when the second writing operation has reached a predetermined phase, changes a second step-up width greater than the first step-up width at least once."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor memory device and controlling method thereof","description":"The control unit performs a first writing operation to obtain a first threshold voltage distribution, and a second writing operation to obtain a second threshold voltage distribution lower than the fi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9767895","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9767895","citation_suggestion":"Patentable. \"Semiconductor memory device and controlling method thereof\" (US-9767895). https://patentable.app/patents/US-9767895","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9767895","json":"https://patentable.app/api/llm-context/US-9767895","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:18:36.663Z"}