{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9768056","patent":{"patent_number":"US-9768056","title":"Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition","assignee":null,"inventors":[],"filing_date":"2014-10-27T00:00:00.000Z","publication_date":"2017-09-19T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":57,"abstract":"A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition","description":"A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductor","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9768056","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9768056","citation_suggestion":"Patentable. \"Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition\" (US-9768056). https://patentable.app/patents/US-9768056","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9768056","json":"https://patentable.app/api/llm-context/US-9768056","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:15:16.139Z"}