{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9768775","patent":{"patent_number":"US-9768775","title":"Methods and apparatuses for sub-threhold clock tree design for optimal power","assignee":null,"inventors":[],"filing_date":"2015-10-27T00:00:00.000Z","publication_date":"2017-09-19T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":20,"abstract":"A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage domains inside a single place and route block. One voltage domain for the “clock tree” buffers and one voltage domain for the other cells at the block. The voltage domain for the “clock tree” buffers that is used is slightly higher than the voltage domain which is used for the other cells. The higher voltage ensures a large reduction of the total number of buffers inside the “clock tree” and the dynamic and static power are reduced dramatically despite the use of slightly higher operating voltage."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods and apparatuses for sub-threhold clock tree design for optimal power","description":"A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage d","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9768775","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9768775","citation_suggestion":"Patentable. \"Methods and apparatuses for sub-threhold clock tree design for optimal power\" (US-9768775). https://patentable.app/patents/US-9768775","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9768775","json":"https://patentable.app/api/llm-context/US-9768775","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:16:35.065Z"}