{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9778982","patent":{"patent_number":"US-9778982","title":"Memory erasure information in cache lines","assignee":null,"inventors":[],"filing_date":"2013-12-09T00:00:00.000Z","publication_date":"2017-10-03T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":14,"abstract":"Example implementations relate to storing memory erasure information in memory devices on a memory module. In example implementations, a memory location associated with an error in a first cache line may be identified. The first cache line may include data read from the memory location, and the memory location may be in a first memory device of a plurality of memory devices on a memory module. A device number corresponding to the first memory device may be written to one of the plurality of memory devices. When the memory location is read for a second cache line, the device number corresponding to the first memory device may be retrieved. The second cache line may include the retrieved device number and data read from the memory location."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory erasure information in cache lines","description":"Example implementations relate to storing memory erasure information in memory devices on a memory module. In example implementations, a memory location associated with an error in a first cache line ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9778982","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9778982","citation_suggestion":"Patentable. \"Memory erasure information in cache lines\" (US-9778982). https://patentable.app/patents/US-9778982","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9778982","json":"https://patentable.app/api/llm-context/US-9778982","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T03:53:34.999Z"}