{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9779020","patent":{"patent_number":"US-9779020","title":"System and method for providing an address cache for memory map learning","assignee":null,"inventors":[],"filing_date":"2014-04-29T00:00:00.000Z","publication_date":"2017-10-03T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":20,"abstract":"A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system provides a one-hot address cache comprising a plurality of one-hot addresses and a host interface to a host memory controller of a host system. Each one-hot address of the plurality of one-hot addresses has a bit width. The plurality of one-hot addresses is configured to store the data associated with a corresponding memory address in an address space of a memory system and provide the data to the host memory controller during a memory map learning process. The plurality of one-hot addresses comprises a zero address of the bit width and a plurality of non-zero addresses of the bit width, and each one-hot address of the plurality of non-zero addresses of the one-hot address cache has only one non-zero address bit of the bit width."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"System and method for providing an address cache for memory map learning","description":"A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system provides a one-hot address cache comprising a plurality of one-hot addresses a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9779020","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9779020","citation_suggestion":"Patentable. \"System and method for providing an address cache for memory map learning\" (US-9779020). https://patentable.app/patents/US-9779020","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9779020","json":"https://patentable.app/api/llm-context/US-9779020","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:04:59.973Z"}