{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9779813","patent":{"patent_number":"US-9779813","title":"Phase change memory array architecture achieving high write/read speed","assignee":null,"inventors":[],"filing_date":"2016-07-28T00:00:00.000Z","publication_date":"2017-10-03T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":19,"abstract":"A memory configured to have data read therefrom is provided. The memory includes a data port including B transmitters disposed in parallel and for transferring data on both rising and falling edges of a clock, a first memory including a first data bus including N lines on which N bits can be transferred, and a second memory including a second data bus including N lines on which N bits can be transferred. The memory includes a data path controller including a data distributor disposed between the first and second memories and being connected to the data port, wherein, on the rising edge, the data distributor distributes a first data segment comprised of B bits from the first data bus to the data port and, on the falling edge, the data distributor distributes a second data segment comprised of B bits from the second data bus to the data port."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Phase change memory array architecture achieving high write/read speed","description":"A memory configured to have data read therefrom is provided. The memory includes a data port including B transmitters disposed in parallel and for transferring data on both rising and falling edges of","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9779813","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9779813","citation_suggestion":"Patentable. \"Phase change memory array architecture achieving high write/read speed\" (US-9779813). https://patentable.app/patents/US-9779813","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9779813","json":"https://patentable.app/api/llm-context/US-9779813","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:21:09.867Z"}