{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9779838","patent":{"patent_number":"US-9779838","title":"Method of improving error checking and correction performance of memory","assignee":null,"inventors":[],"filing_date":"2015-08-28T00:00:00.000Z","publication_date":"2017-10-03T00:00:00.000Z","cpc_codes":["G11C","G06F","G11C","G11C","G11C"],"num_claims":16,"abstract":"A method of improving an error checking and correction performance of a memory includes replacing a defective column including a defective memory cell of the memory cell array with a spare column of a the spare cell array, wherein the memory cell array includes memory cells in a matrix and the spare cell array includes spare memory cells in a matrix to be replaced for defective memory cells; storing check bits of error correction code in at least one memory cell of the defective column; storing defect information regarding a defect of the defective memory cell; determining whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory, based on the defect information; and performing error checking and correction on the memory using a memory cell selected based on a result of determining whether the at least one memory cell storing the check bits is to be used."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of improving error checking and correction performance of memory","description":"A method of improving an error checking and correction performance of a memory includes replacing a defective column including a defective memory cell of the memory cell array with a spare column of a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9779838","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9779838","citation_suggestion":"Patentable. \"Method of improving error checking and correction performance of memory\" (US-9779838). https://patentable.app/patents/US-9779838","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9779838","json":"https://patentable.app/api/llm-context/US-9779838","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:22:58.163Z"}