{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9780072","patent":{"patent_number":"US-9780072","title":"3D semiconductor package interposer with die cavity","assignee":null,"inventors":[],"filing_date":"2016-05-13T00:00:00.000Z","publication_date":"2017-10-03T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"3D semiconductor package interposer with die cavity","description":"Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mo","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9780072","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9780072","citation_suggestion":"Patentable. \"3D semiconductor package interposer with die cavity\" (US-9780072). https://patentable.app/patents/US-9780072","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9780072","json":"https://patentable.app/api/llm-context/US-9780072","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:40:11.574Z"}