{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9785371","patent":{"patent_number":"US-9785371","title":"Power-reducing memory subsystem having a system cache and local resource management","assignee":null,"inventors":[],"filing_date":"2016-03-27T00:00:00.000Z","publication_date":"2017-10-10T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G11C","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":30,"abstract":"Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem adjusts access to the DRAM based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Power-reducing memory subsystem having a system cache and local resource management","description":"Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a p","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9785371","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9785371","citation_suggestion":"Patentable. \"Power-reducing memory subsystem having a system cache and local resource management\" (US-9785371). https://patentable.app/patents/US-9785371","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9785371","json":"https://patentable.app/api/llm-context/US-9785371","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T14:50:51.592Z"}