{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9785530","patent":{"patent_number":"US-9785530","title":"Method, device, and system for processing PCIe link fault","assignee":null,"inventors":[],"filing_date":"2015-07-22T00:00:00.000Z","publication_date":"2017-10-10T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F"],"num_claims":12,"abstract":"In a Peripheral Component Interconnect Express (PCIe) system, a first PCIe apparatus determines that at least one of lanes of a link between the first PCIe apparatus and a second PCIe apparatus is disabled, wherein the link includes M lanes numbered in a first order. Based upon the determination, the first PCIe apparatus obtains a number N indicating a number of available lanes of the link by performing a lane negotiation with the second PCIe apparatus. Then, a processor determines that N<M/2. Based upon the determination, the first PCIe apparatus re-numbers at least some of the lanes of the link in a reverse order opposite to the first order as instructed by the processor. At last, the first PCIe apparatus continue to perform a negotiation with the second PCIe apparatus to obtain available lanes."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method, device, and system for processing PCIe link fault","description":"In a Peripheral Component Interconnect Express (PCIe) system, a first PCIe apparatus determines that at least one of lanes of a link between the first PCIe apparatus and a second PCIe apparatus is dis","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9785530","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9785530","citation_suggestion":"Patentable. \"Method, device, and system for processing PCIe link fault\" (US-9785530). https://patentable.app/patents/US-9785530","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9785530","json":"https://patentable.app/api/llm-context/US-9785530","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:19:43.871Z"}