{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9786338","patent":{"patent_number":"US-9786338","title":"Multiple register memory access instructions, processors, methods, and systems","assignee":null,"inventors":[],"filing_date":"2016-08-16T00:00:00.000Z","publication_date":"2017-10-10T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G06F"],"num_claims":20,"abstract":"A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Multiple register memory access instructions, processors, methods, and systems","description":"A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9786338","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9786338","citation_suggestion":"Patentable. \"Multiple register memory access instructions, processors, methods, and systems\" (US-9786338). https://patentable.app/patents/US-9786338","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9786338","json":"https://patentable.app/api/llm-context/US-9786338","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:17:02.437Z"}