{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9786521","patent":{"patent_number":"US-9786521","title":"Chip package method for reducing chip leakage current","assignee":null,"inventors":[],"filing_date":"2016-11-01T00:00:00.000Z","publication_date":"2017-10-10T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":10,"abstract":"A chip package method can include: forming bonding pins on a first region of a first surface of a carrier; forming an insulating layer on an inactive face of a chip, where the inactive face of the chip is opposite to an active face of the chip; pasting the chip on a second region of the first surface of the carrier by the insulating layer; electrically coupling electrodes on the active face of the chip to the bonding pins by conductive wires; forming an enclosure to cover the chip and the bonding pins by a molding process; and peeling away the carrier from the enclosure to expose the bonding pins and the insulating layer on a surface of the enclosure."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Chip package method for reducing chip leakage current","description":"A chip package method can include: forming bonding pins on a first region of a first surface of a carrier; forming an insulating layer on an inactive face of a chip, where the inactive face of the chi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9786521","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9786521","citation_suggestion":"Patentable. \"Chip package method for reducing chip leakage current\" (US-9786521). https://patentable.app/patents/US-9786521","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9786521","json":"https://patentable.app/api/llm-context/US-9786521","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:21:42.825Z"}