{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9792115","patent":{"patent_number":"US-9792115","title":"Super multiply add (super MADD) instructions with three scalar terms","assignee":null,"inventors":[],"filing_date":"2011-12-23T00:00:00.000Z","publication_date":"2017-10-17T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":21,"abstract":"A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Super multiply add (super MADD) instructions with three scalar terms","description":"A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a thi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9792115","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9792115","citation_suggestion":"Patentable. \"Super multiply add (super MADD) instructions with three scalar terms\" (US-9792115). https://patentable.app/patents/US-9792115","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9792115","json":"https://patentable.app/api/llm-context/US-9792115","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T03:48:17.994Z"}