{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9792395","patent":{"patent_number":"US-9792395","title":"Memory utilization in a circuit design","assignee":null,"inventors":[],"filing_date":"2016-02-02T00:00:00.000Z","publication_date":"2017-10-17T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":20,"abstract":"The disclosed approaches compile a hierarchical representation of a circuit design into a flattened netlist and store the flattened netlist a memory circuit. The circuit design instantiates a plurality of memory blocks of a target device and specifies logic circuits that access the plurality of memory blocks, respectively. The flattened netlist is modified by determining a subset of the plurality of memory blocks. The quantity of memory reserved in each memory block of the subset is less than a capacity of said each memory block. One memory block is instantiated, for a pair of the memory blocks of the subset, in place of each memory block of the pair in the flattened netlist in the memory circuit. A portion of the flattened netlist that specifies the logic circuits that access each memory block of the pair is modified to access the one memory block instead of each memory block of the pair."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory utilization in a circuit design","description":"The disclosed approaches compile a hierarchical representation of a circuit design into a flattened netlist and store the flattened netlist a memory circuit. The circuit design instantiates a pluralit","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9792395","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9792395","citation_suggestion":"Patentable. \"Memory utilization in a circuit design\" (US-9792395). https://patentable.app/patents/US-9792395","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9792395","json":"https://patentable.app/api/llm-context/US-9792395","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:43:49.795Z"}