{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9792967","patent":{"patent_number":"US-9792967","title":"Managing semiconductor memory array leakage current","assignee":null,"inventors":[],"filing_date":"2016-06-13T00:00:00.000Z","publication_date":"2017-10-17T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":14,"abstract":"A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local evaluation circuit to a global bit line (GBL) of the global evaluation circuit. The global evaluation circuit can include a holding circuit. The wake transistor can be turned on in response to a read signal, and remain on while the GBL is precharged to a logical “high” voltage. Memory cells connected to the at least one local bit line can be addressed, and the local bit line can be pulled to a logical “low” voltage for a first time period. The GBL can be pulled to a logical low voltage for a second time period, and the holding circuit polarity can be reversed during a third time period."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Managing semiconductor memory array leakage current","description":"A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9792967","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9792967","citation_suggestion":"Patentable. \"Managing semiconductor memory array leakage current\" (US-9792967). https://patentable.app/patents/US-9792967","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9792967","json":"https://patentable.app/api/llm-context/US-9792967","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:02:35.455Z"}