{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9793210","patent":{"patent_number":"US-9793210","title":"Power line layout structure of semiconductor device and method for forming the same","assignee":null,"inventors":[],"filing_date":"2016-06-21T00:00:00.000Z","publication_date":"2017-10-17T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L"],"num_claims":13,"abstract":"A power line layout structure of a semiconductor device and a method for forming the same are disclosed. The power line layout structure of the semiconductor device includes a first block region including a plurality of first and second power lines, a second block region including a plurality of first and second power lines spaced apart from the first block region by a predetermined distance. Further, a first connection pattern arranged in a boundary region between the first and second block region, and formed to interconnect the first power line of the first block region and the first power line of the second block region. Still further, a second connection pattern arranged in a boundary region between the first and second block regions, and formed to interconnect the first and second block region power lines, wherein the first and second connection patterns are formed over different layers."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Power line layout structure of semiconductor device and method for forming the same","description":"A power line layout structure of a semiconductor device and a method for forming the same are disclosed. The power line layout structure of the semiconductor device includes a first block region inclu","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9793210","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9793210","citation_suggestion":"Patentable. \"Power line layout structure of semiconductor device and method for forming the same\" (US-9793210). https://patentable.app/patents/US-9793210","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9793210","json":"https://patentable.app/api/llm-context/US-9793210","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:19:21.432Z"}