{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9793290","patent":{"patent_number":"US-9793290","title":"Method of manufacturing semiconductor memory device having charge accumulation layer positioned between control gate electrode and semiconductor layer","assignee":null,"inventors":[],"filing_date":"2016-03-16T00:00:00.000Z","publication_date":"2017-10-17T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":5,"abstract":"According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of manufacturing semiconductor memory device having charge accumulation layer positioned between control gate electrode and semiconductor layer","description":"According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electro","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9793290","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9793290","citation_suggestion":"Patentable. \"Method of manufacturing semiconductor memory device having charge accumulation layer positioned between control gate electrode and semiconductor layer\" (US-9793290). https://patentable.app/patents/US-9793290","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9793290","json":"https://patentable.app/api/llm-context/US-9793290","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:19:21.526Z"}