{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9798352","patent":{"patent_number":"US-9798352","title":"Circuits for and methods of implementing a design for testing and debugging with dual-edge clocking","assignee":null,"inventors":[],"filing_date":"2015-11-12T00:00:00.000Z","publication_date":"2017-10-24T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":20,"abstract":"A circuit for implementing a scan chain in an integrated circuit having a clock domain crossing is described. The circuit comprises a first dual-edge storage circuit configured to receive an input signal at a scan input and to receive a first clock signal in a first clock domain at a clock input; a storage element having a data input configured to receive an output of the first dual-edge storage circuit; a second dual-edge storage circuit configured to receive an output of the storage element at a scan input and to receive a second clock signal in a second clock domain at a clock input; and a pulse generator configured to provide, to a clock input of the storage element, a pulse signal having a pulse width selected to enable the second dual-edge storage element to store the output of the first dual-edge storage element."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Circuits for and methods of implementing a design for testing and debugging with dual-edge clocking","description":"A circuit for implementing a scan chain in an integrated circuit having a clock domain crossing is described. The circuit comprises a first dual-edge storage circuit configured to receive an input sig","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9798352","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9798352","citation_suggestion":"Patentable. \"Circuits for and methods of implementing a design for testing and debugging with dual-edge clocking\" (US-9798352). https://patentable.app/patents/US-9798352","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9798352","json":"https://patentable.app/api/llm-context/US-9798352","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T15:30:44.149Z"}