{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9798591","patent":{"patent_number":"US-9798591","title":"Method, apparatus, and chip for implementing mutually-exclusive operation of multiple threads","assignee":null,"inventors":[],"filing_date":"2015-10-01T00:00:00.000Z","publication_date":"2017-10-24T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":12,"abstract":"Multiple lock assemblies are distributed on a chip, each lock assembly manage a lock application message for applying for a lock and a lock release message for releasing a lock that are sent by one small core. Specifically, embodiments include receiving a lock message sent by a small core, where the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; calculating, using the memory address of the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method, apparatus, and chip for implementing mutually-exclusive operation of multiple threads","description":"Multiple lock assemblies are distributed on a chip, each lock assembly manage a lock application message for applying for a lock and a lock release message for releasing a lock that are sent by one sm","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9798591","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9798591","citation_suggestion":"Patentable. \"Method, apparatus, and chip for implementing mutually-exclusive operation of multiple threads\" (US-9798591). https://patentable.app/patents/US-9798591","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9798591","json":"https://patentable.app/api/llm-context/US-9798591","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:26:30.033Z"}