{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9799595","patent":{"patent_number":"US-9799595","title":"Careless wiring substrate having an insulation layer with a bulged covering portion and semiconductor device thereof","assignee":null,"inventors":[],"filing_date":"2016-10-19T00:00:00.000Z","publication_date":"2017-10-24T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":7,"abstract":"A wiring substrate is provided with a wiring pattern including a pad and a circuit pattern. The pad is formed in a mounting region where an electronic component is mounted, and the circuit pattern extends in a planar direction from the pad. An insulation layer covers a lower surface of the wiring pattern and a side surface of the wiring pattern and partially exposes an upper surface of the wiring pattern. The insulation layer includes a covering portion that continuously covers an entire peripheral portion of the upper surface of the wiring pattern. The insulation layer includes an upper surface located upward from the upper surface of the wiring pattern."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Careless wiring substrate having an insulation layer with a bulged covering portion and semiconductor device thereof","description":"A wiring substrate is provided with a wiring pattern including a pad and a circuit pattern. The pad is formed in a mounting region where an electronic component is mounted, and the circuit pattern ext","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9799595","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9799595","citation_suggestion":"Patentable. \"Careless wiring substrate having an insulation layer with a bulged covering portion and semiconductor device thereof\" (US-9799595). https://patentable.app/patents/US-9799595","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9799595","json":"https://patentable.app/api/llm-context/US-9799595","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:03:36.620Z"}