{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9799661","patent":{"patent_number":"US-9799661","title":"SRAM bitcell structures facilitating biasing of pull-down transistors","assignee":null,"inventors":[],"filing_date":"2017-01-03T00:00:00.000Z","publication_date":"2017-10-24T00:00:00.000Z","cpc_codes":["G11C","H01L","G11C"],"num_claims":19,"abstract":"Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pull-down (PD1) transistor and a second pull-down (PD2) transistor. The at least one CBP facilitates biasing at least one of the PD1 and PD2 transistors during at least one of a read, write or standby operation of the structures."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"SRAM bitcell structures facilitating biasing of pull-down transistors","description":"Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9799661","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9799661","citation_suggestion":"Patentable. \"SRAM bitcell structures facilitating biasing of pull-down transistors\" (US-9799661). https://patentable.app/patents/US-9799661","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9799661","json":"https://patentable.app/api/llm-context/US-9799661","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:41:26.814Z"}