{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9804845","patent":{"patent_number":"US-9804845","title":"Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor","assignee":null,"inventors":[],"filing_date":"2015-11-24T00:00:00.000Z","publication_date":"2017-10-31T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":21,"abstract":"An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory, where the specified load instruction comprises a load instruction resulting from execution of an x86 special bus cycle. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor","description":"An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specifie","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9804845","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9804845","citation_suggestion":"Patentable. \"Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor\" (US-9804845). https://patentable.app/patents/US-9804845","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9804845","json":"https://patentable.app/api/llm-context/US-9804845","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:01:37.108Z"}