{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9804849","patent":{"patent_number":"US-9804849","title":"Space reduction in processor stressmark generation","assignee":null,"inventors":[],"filing_date":"2015-10-20T00:00:00.000Z","publication_date":"2017-10-31T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":13,"abstract":"An aspect includes pruning a design space when generating a maximum power stressmark. A multi-stage design space search process is performed. Each stage includes calculating a number of instructions per cycle (IPC) for each instruction sequence in a set of instruction sequences that place a power stress on a system under analysis, removing one or more of the instruction sequences having an IPC lower than a pruning threshold from the set, evaluating at least one power metric of the remaining instruction sequences in the set, removing one or more of the instruction sequences having at least one power metric evaluated outside of one or more pruning ranges from the set, and passing the remaining instruction sequences in the set to a next stage. A maximum power stressmark is generated based on the evaluating of the at least one power metric from a final stage."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Space reduction in processor stressmark generation","description":"An aspect includes pruning a design space when generating a maximum power stressmark. A multi-stage design space search process is performed. Each stage includes calculating a number of instructions p","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9804849","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9804849","citation_suggestion":"Patentable. \"Space reduction in processor stressmark generation\" (US-9804849). https://patentable.app/patents/US-9804849","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9804849","json":"https://patentable.app/api/llm-context/US-9804849","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:22:03.884Z"}