{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9805825","patent":{"patent_number":"US-9805825","title":"Memory error capture logic","assignee":null,"inventors":[],"filing_date":"2015-08-24T00:00:00.000Z","publication_date":"2017-10-31T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"A built-in self test (BIST) may be performed on a device memory having two memory portions that are symmetrical (e.g., two symmetric halves of the device memory). The BIST may be run on the first memory portion. Error logic output from the first memory portion is captured (stored) in the second memory portion during the BIST run process. Error logic output from the first memory portion may include error data and an address of the memory error in the first memory portion. As the first and second memory portions are symmetric, the memory errors captured (stored) in the second memory portion are located at identical locations to the location of the memory errors in the first memory portion. A memory dump from the second memory portion after the BIST may provide a map of the memory errors in the first memory portion."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory error capture logic","description":"A built-in self test (BIST) may be performed on a device memory having two memory portions that are symmetrical (e.g., two symmetric halves of the device memory). The BIST may be run on the first memo","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9805825","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9805825","citation_suggestion":"Patentable. \"Memory error capture logic\" (US-9805825). https://patentable.app/patents/US-9805825","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9805825","json":"https://patentable.app/api/llm-context/US-9805825","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T14:41:01.409Z"}