{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9811113","patent":{"patent_number":"US-9811113","title":"System and method for synchronization among multiple PLL-based clock signals","assignee":null,"inventors":[],"filing_date":"2016-07-12T00:00:00.000Z","publication_date":"2017-11-07T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":9,"abstract":"A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"System and method for synchronization among multiple PLL-based clock signals","description":"A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common freq","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9811113","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9811113","citation_suggestion":"Patentable. \"System and method for synchronization among multiple PLL-based clock signals\" (US-9811113). https://patentable.app/patents/US-9811113","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9811113","json":"https://patentable.app/api/llm-context/US-9811113","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T15:40:33.349Z"}