{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9811148","patent":{"patent_number":"US-9811148","title":"Static power reduction in caches using deterministic naps","assignee":null,"inventors":[],"filing_date":"2017-02-14T00:00:00.000Z","publication_date":"2017-11-07T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":2,"abstract":"The dNap architecture is able to accurately transition cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Static power reduction in caches using deterministic naps","description":"The dNap architecture is able to accurately transition cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only ca","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9811148","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9811148","citation_suggestion":"Patentable. \"Static power reduction in caches using deterministic naps\" (US-9811148). https://patentable.app/patents/US-9811148","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9811148","json":"https://patentable.app/api/llm-context/US-9811148","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:18:51.604Z"}