{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9811625","patent":{"patent_number":"US-9811625","title":"Computer-implemented method and computer program for generating a layout of a circuit block of an integrated circuit","assignee":null,"inventors":[],"filing_date":"2015-04-28T00:00:00.000Z","publication_date":"2017-11-07T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":22,"abstract":"A computer implemented method and a computer program for generating a layout of a circuit block of an integrated circuit are provided. Input data is received identifying a plurality of circuit elements and interconnections required to implement the circuit block, and the method also has access to a cell library providing a plurality of standard cells, where each standard cell defines a corresponding circuit element using transistors, the transistors comprising n-type transistors and p-type transistors. A plurality of rows are formed within which to place standard cells from the cell library in order to implement the circuit block, the plurality of rows including at least one body biased row in which a body bias is to be applied in respect of either the n-type transistors or the p-type transistors provided by the standard cells placed in that body biased row. Constraint data is specified identifying a subset of the standard cells that are allowed to be placed in each body biased row, and the layout is then generated by placing standard cells within the plurality of rows having regard to the input data, an indication of each body biased row, and the constraint data for each body biased row. This enables a significant improvement in the benefits that can be achieved through the use of body biasing mechanisms, for example allowing a significant increase in switching speed of the circuit block to be achieved, without a significant increase in leakage current."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Computer-implemented method and computer program for generating a layout of a circuit block of an integrated circuit","description":"A computer implemented method and a computer program for generating a layout of a circuit block of an integrated circuit are provided. Input data is received identifying a plurality of circuit element","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9811625","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9811625","citation_suggestion":"Patentable. \"Computer-implemented method and computer program for generating a layout of a circuit block of an integrated circuit\" (US-9811625). https://patentable.app/patents/US-9811625","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9811625","json":"https://patentable.app/api/llm-context/US-9811625","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:04:39.097Z"}