{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9811626","patent":{"patent_number":"US-9811626","title":"Method of designing layout of semiconductor device","assignee":null,"inventors":[],"filing_date":"2015-09-09T00:00:00.000Z","publication_date":"2017-11-07T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":19,"abstract":"A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning process by a layout design system. The method also includes allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the self-align double patterning process."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of designing layout of semiconductor device","description":"A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patter","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9811626","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9811626","citation_suggestion":"Patentable. \"Method of designing layout of semiconductor device\" (US-9811626). https://patentable.app/patents/US-9811626","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9811626","json":"https://patentable.app/api/llm-context/US-9811626","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:45:10.801Z"}