{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9812176","patent":{"patent_number":"US-9812176","title":"Memory structure","assignee":null,"inventors":[],"filing_date":"2016-11-30T00:00:00.000Z","publication_date":"2017-11-07T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","H01L"],"num_claims":19,"abstract":"A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer≧2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=⅕ to ½. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines. M array regions of the N array regions are configured to operate simultaneously. M is an integer. M/N=½ or 1."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory structure","description":"A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer≧2. Each of the N array regions includes a 3D array of a plurality of memory","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9812176","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9812176","citation_suggestion":"Patentable. \"Memory structure\" (US-9812176). https://patentable.app/patents/US-9812176","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9812176","json":"https://patentable.app/api/llm-context/US-9812176","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T15:43:21.769Z"}