{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9812183","patent":{"patent_number":"US-9812183","title":"Read latency reduction in a memory device","assignee":null,"inventors":[],"filing_date":"2016-03-04T00:00:00.000Z","publication_date":"2017-11-07T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":6,"abstract":"A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Read latency reduction in a memory device","description":"A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an addr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9812183","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9812183","citation_suggestion":"Patentable. \"Read latency reduction in a memory device\" (US-9812183). https://patentable.app/patents/US-9812183","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9812183","json":"https://patentable.app/api/llm-context/US-9812183","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:21:10.672Z"}