{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9812403","patent":{"patent_number":"US-9812403","title":"Reducing wafer warpage during wafer processing","assignee":null,"inventors":[],"filing_date":"2015-08-24T00:00:00.000Z","publication_date":"2017-11-07T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":6,"abstract":"A manufacturing method of a semiconductor device that can reduce warpage during wafer processing. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Reducing wafer warpage during wafer processing","description":"A manufacturing method of a semiconductor device that can reduce warpage during wafer processing. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. Th","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9812403","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9812403","citation_suggestion":"Patentable. \"Reducing wafer warpage during wafer processing\" (US-9812403). https://patentable.app/patents/US-9812403","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9812403","json":"https://patentable.app/api/llm-context/US-9812403","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:04:29.221Z"}