{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9814106","patent":{"patent_number":"US-9814106","title":"Backlight driver chip incorporating a phase lock loop (PLL) with programmable offset/delay and seamless operation","assignee":null,"inventors":[],"filing_date":"2014-09-30T00:00:00.000Z","publication_date":"2017-11-07T00:00:00.000Z","cpc_codes":["G09G","G09G","G09G","G09G","G09G"],"num_claims":19,"abstract":"The embodiments discussed herein relate to systems, methods, and apparatus for synchronizing a pulse width modulation (PWM) dimming clock signal with a frame rate signal, line sync signal, and/or a horizontal sync signal of a display device. The PWM dimming clock signal can be generated by a synchronization block having a programmable offset/delay. The programmable offset/delay can control the offset or phase difference between an input and an output clock signal of the synchronization block. Depending on the clock rate of PWM dimming and/or panel resolution, the phase/offset delay can be adjusted to achieve the optimum front of screen performance. Additionally, an input clock generator/missing pulse detection block can output a programmed clock signal to the synchronization block in case of a missing external clock, or insert a pulse when there is a missing pulse detected."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Backlight driver chip incorporating a phase lock loop (PLL) with programmable offset/delay and seamless operation","description":"The embodiments discussed herein relate to systems, methods, and apparatus for synchronizing a pulse width modulation (PWM) dimming clock signal with a frame rate signal, line sync signal, and/or a ho","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9814106","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9814106","citation_suggestion":"Patentable. \"Backlight driver chip incorporating a phase lock loop (PLL) with programmable offset/delay and seamless operation\" (US-9814106). https://patentable.app/patents/US-9814106","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9814106","json":"https://patentable.app/api/llm-context/US-9814106","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:42:49.728Z"}