{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9817660","patent":{"patent_number":"US-9817660","title":"Method for reducing execution jitter in multi-core processors within an information handling system","assignee":null,"inventors":[],"filing_date":"2015-05-28T00:00:00.000Z","publication_date":"2017-11-14T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":20,"abstract":"A method of reducing execution jitter includes a processor having several cores and control logic that receives core configuration parameters. Control logic determines if a first set of cores are selected to be disabled. If none of the cores is selected to be disabled, the control logic determines if a second set of cores is selected to be jitter controlled. If the second set of cores is selected to be jitter controlled, the second set of cores is set to a first operating state. If the first set of cores is selected to be disabled, the control logic determines a second operating state for a third set of enabled cores. The control logic determines if the third set of enabled cores is jitter controlled, and if the third set of enabled cores is jitter controlled, the control logic sets the third set of enabled cores to the second operating state."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for reducing execution jitter in multi-core processors within an information handling system","description":"A method of reducing execution jitter includes a processor having several cores and control logic that receives core configuration parameters. Control logic determines if a first set of cores are sele","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9817660","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9817660","citation_suggestion":"Patentable. \"Method for reducing execution jitter in multi-core processors within an information handling system\" (US-9817660). https://patentable.app/patents/US-9817660","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9817660","json":"https://patentable.app/api/llm-context/US-9817660","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:02:30.006Z"}