{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9817936","patent":{"patent_number":"US-9817936","title":"Methods for minimizing layout area of IC","assignee":null,"inventors":[],"filing_date":"2015-06-17T00:00:00.000Z","publication_date":"2017-11-14T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":26,"abstract":"A method for minimizing layout area of IC is provided. A plurality of first tiles of an initial floor plan are obtained according to a plurality of partitions and channels of the initial floor plan. Each first tile between the partition and the channel has a fixed tile property being the partition or the channel. Each second tile between at least one of the partitions and at least one of the channels has a changeable tile property which can be changed between the at least one partition and the at least one channel. A specific area path of the layout area is obtained according to the partitions, the channels and the routing densities corresponding to the channels. The changeable tile properties of the second tiles are changed according to the specific area path, to re-shape the partitions and re-route the nets within the channels."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods for minimizing layout area of IC","description":"A method for minimizing layout area of IC is provided. A plurality of first tiles of an initial floor plan are obtained according to a plurality of partitions and channels of the initial floor plan. E","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9817936","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9817936","citation_suggestion":"Patentable. \"Methods for minimizing layout area of IC\" (US-9817936). https://patentable.app/patents/US-9817936","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9817936","json":"https://patentable.app/api/llm-context/US-9817936","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:45:16.987Z"}