{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9818625","patent":{"patent_number":"US-9818625","title":"Stacked semiconductor die assemblies with thermal spacers and associated systems and methods","assignee":null,"inventors":[],"filing_date":"2016-03-02T00:00:00.000Z","publication_date":"2017-11-14T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":18,"abstract":"Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Stacked semiconductor die assemblies with thermal spacers and associated systems and methods","description":"Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive ca","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9818625","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9818625","citation_suggestion":"Patentable. \"Stacked semiconductor die assemblies with thermal spacers and associated systems and methods\" (US-9818625). https://patentable.app/patents/US-9818625","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9818625","json":"https://patentable.app/api/llm-context/US-9818625","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T13:54:22.935Z"}