{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9818656","patent":{"patent_number":"US-9818656","title":"Devices and methods for testing integrated circuit devices","assignee":null,"inventors":[],"filing_date":"2017-05-23T00:00:00.000Z","publication_date":"2017-11-14T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A method of testing includes attaching a first and second die to first and second die sites of a lead frame and forming a plurality of wire bonds coupling a plurality of pins of the first die site to the first die and a plurality of pins of the second die site to the second die. The first and second die are encapsulated. An isolation cut is performed to isolate the plurality of pins of the first die site from the plurality of pins of the second die site, while maintaining electrical connection between the first tie bar of the first die site and the first tie bar of the second die site. The first and second die are tested while providing a first power supply source to the first and second die via the first tie bars. After testing, the dies sites are fully singulated to result in packaged IC device."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Devices and methods for testing integrated circuit devices","description":"A method of testing includes attaching a first and second die to first and second die sites of a lead frame and forming a plurality of wire bonds coupling a plurality of pins of the first die site to ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9818656","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9818656","citation_suggestion":"Patentable. \"Devices and methods for testing integrated circuit devices\" (US-9818656). https://patentable.app/patents/US-9818656","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9818656","json":"https://patentable.app/api/llm-context/US-9818656","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:56:15.336Z"}